`include "ysyx_23060189_cpu.svh"
`include "ysyx_23060189_isa.svh"

module ysyx_23060189_BrCond(
  input  wire [`ysyx_23060189_BrTypeBus] br_type,
  input  wire [`ysyx_23060189_DataBus]   rs1_data,
  input  wire [`ysyx_23060189_DataBus]   rs2_data,
  output wire br_taken
);

  MuxKeyWithDefault #(7, `ysyx_23060189_BR_TYPE_W, 1) Mux (br_taken, br_type, 1'b0,{
    `ysyx_23060189_BR_XXX,  1'b0,
    `ysyx_23060189_BR_BNE,  rs1_data != rs2_data ? 1'b1 : 1'b0,
    `ysyx_23060189_BR_BEQ,  rs1_data == rs2_data ? 1'b1 : 1'b0,
    `ysyx_23060189_BR_BGE,  $signed(rs1_data) >= $signed(rs2_data) ? 1'b1 : 1'b0,
    `ysyx_23060189_BR_BGEU, rs1_data >= rs2_data ? 1'b1 : 1'b0,
    `ysyx_23060189_BR_BLTU, rs1_data < rs2_data ? 1'b1 : 1'b0,
    `ysyx_23060189_BR_BLT,  $signed(rs1_data) < $signed(rs2_data) ? 1'b1 : 1'b0
  });

endmodule
